1. Technical Field
The present invention relates to cache memories in general and, in particular, to a method and apparatus for casting out data from a cache memory within a data processing system. Still more particularly, the present invention relates to a method and apparatus for casting out data within a cache memory hierarchy for a multiprocessor data processing system.
2. Description of the Prior Art
In a symmetric multiprocessor (SMP) data processing system, all of the processing units are generally identical; that is, they all utilize a common set or subset of instructions and protocols to operate and, generally, have the same architecture. Each processing unit includes a processor core having multiple registers and execution units for carrying out program instructions. Each processing unit may also have a multi-level cache memory hierarchy.
A multi-level cache memory hierarchy is a cache memory system consisting of several levels of cache memories, each level having a different size and speed. Typically, the first level cache memory, commonly known as the level one (L1) cache, has the fastest access time and the highest cost per bit. The remaining levels of cache memories, such as level two (L2) caches, level three (L3) caches, etc., have a relatively slower access time, but also a relatively lower cost per bit. Typically, each lower cache memory level has a progressively slower access time and a lower per-bit cost.
Because there are many possible operating scenarios in which data can be transferred between cache memory hierarchies, and between cache levels within a cache memory hierarchy in a multiprocessor data processing system, it is important to efficiently transfer data from one cache to another. The present disclosure is related to a method and apparatus for casting out data within a cache memory hierarchy of a multiprocessor data processing system. Data may be casted out from one cache to another cache, typically a lower level cache, for data deallocation or other reasons.